The present invention relates to an active matrix display apparatus typified by an LCD, and particularly to configuration of a vertical driving circuit for driving a pixel array in a form of a matrix.
FIG. 5 is a perspective view of a general configuration of an active matrix display apparatus. As shown in FIG. 5, the conventional display apparatus has a panel structure including a pair of substrates 1 and 2 and a liquid crystal 3 retained between the substrates 1 and 2. A counter electrode is formed on the upper substrate 2. A pixel array unit 4 and a driving circuit unit are formed in an integrated manner on the lower substrate 1. The driving circuit unit is divided into a vertical driving circuit 5 and a horizontal driving circuit 6. Terminals 7 for connection to the outside are formed at an upper end on a periphery of the substrate. The terminals 7 are connected to the vertical driving circuit 5 and the horizontal driving circuit 6 via wiring 8. The pixel array unit 4 has gate lines G and signal lines S formed therein. Pixel electrodes 9 and thin film transistors 10 for driving the pixel electrodes are formed at intersections of the gate lines G and the signal lines S. A pixel P is formed by a combination of a pixel electrode 9 and a thin film transistor 10. The thin film transistor 10 has a gate electrode connected to a corresponding gate line G, a drain region connected to a corresponding pixel electrode 9, and a source region connected to a corresponding signal line S. The gate lines G are connected to the vertical driving circuit 5, whereas the signal lines S are connected to the horizontal driving circuit 6. The vertical driving circuit 5 sequentially selects pixels P via the gate lines G. The horizontal driving circuit 6 writes a video signal to the selected pixels P via the signal lines S.
As definition of LCDs becomes higher, the pixels are reduced in size. With the reduction in size of the pixels, the vertical driving circuit also needs to be reduced in size. The vertical driving circuit generally comprises a multistage-connected shift register, with each stage corresponding to one gate line. By a shift pulse sequentially outputted from each stage of the shift register, the vertical driving circuit selects a pixel row connected to the corresponding gate line on a line-sequential basis. However, since the reduction in size of the pixels decreases an arranging pitch of the gate lines, one stage of the shift register cannot correspond to a space of one pixel corresponding to one gate line.
Accordingly, a vertical driving circuit in which one stage of a shift register is provided for two gate lines has been developed, which is referred to as a decoding type vertical driving circuit. The decoding type vertical driving circuit logically processes a shift pulse outputted from one stage of the shift register and thereby generates drive pulses for two gate lines. The decoding type vertical driving circuit uses a logical gate circuit corresponding to each stage of the shift register to sequentially process the shift pulse according to externally supplied clock pulses. However, a part of the conventionally used logical gate circuit which part corresponds to a first stage of the shift register cannot be made completely the same as parts corresponding to succeeding stages of the shift register, so that a first few pulses are not normal pulses but are irregular drive pulses. Therefore rows of pixels corresponding to a first few gate lines are not selected regularly on a line-sequential basis, and the horizontal driving circuit cannot correctly write a video signal to the first few rows of pixels. Thus a configuration with the conventional decoding type vertical driving circuit uses the first few rows of pixels as dummies to which the video signal is not actually written. However, when the dummy pixel rows are provided, a corresponding effective display area on the substrate is sacrificed, which is a problem to be solved.